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並前往https://community.intel.com/t5/Intel-Quartus-Prime-Software/%E5%93%88%E5%9B%89%E5%A4%A7%E5%AE%B6%E5%A5%BD-%E6%88%91%E6%83%B3%E5%95%8F%E5%A6%82%E4%BD%95%E5%9C%A8Quartus-II%E4%B8%8A%E7%94%A2%E7%94%9F%E5%82%B3%E6%92%AD%E5%BB%B6%E9%81%B2-%E4%BD%BF%E7%94%A8verilog-10%E5%AF%AB%E6%B3%95%E5%9C%A8%E7%B7%A8%E8%AD%AF%E6%99%82%E6%9C%83%E8%A2%AB%E5%BF%BD%E7%95%A5/m-p/666584

我想問如何在Quartus II上產生傳播延遲，使用verilog #10寫法 ...

Propagation delays in Verilog like #10 are non-synthesizable and Quartus ignores delays coded in Verilog. If you really need to introduce a delay in a ...

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