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並前往https://verificationacademy.com/forums/systemverilog/delay-not-working-expected-system-verilog-class-timescale-issue

#delay is not working as expected in system verilog class ...

I add #2000ns in my class(actually it's a UVM test sequence), but it seems that it does not delay 2000ns, I print time before and after this ...

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