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[爆卦]verilog # delay是什麼？優點缺點精華區懶人包

為什麼這篇verilog # delay鄉民發文收入到精華區：因為在verilog # delay這個討論話題中，有許多相關的文章在討論，這篇最有參考價值！作者Emeth (Emeth)看板Electronics標題[問題] verilog delay問題...

作者Emeth (Emeth)

看板Electronics

標題[問題] verilog delay問題

時間Wed Nov 7 16:18:59 2018

大家好，我有一個關於delay的問題，不知何解，

程式碼如下：
https://i.imgur.com/Es4FI5x.png

我根據程式碼畫出來的波形圖是長這樣：
https://i.imgur.com/s3TT4iB.png

然後實際跑出來的結果是這樣：
https://i.imgur.com/bkf0QxD.png

我的問題是：為什麼D在150ns~170ns之間沒有變成1？

我的想法是，因為在110ns時，E從1變成0，
那麼在delay 40ns以後，在150ns的時候，
D應該是做0和0的nor(因為在110ns時，w1和E都是0)，所以D在150ns時變成1。

請問我是哪裡想錯了？

謝謝。

--
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→ wildwolf: 110ns的E變化，要等到 110+40=150ns 的時候，才去看w1和 11/07 16:32

→ wildwolf: E的值，所以在 150ns 的時候，D的值是 0 11/07 16:33

我明白了，謝謝！

不過這樣我又有幾個問題：
1. 所以有delay的gate，例如我程式裡的nor gate，
只有在input發生改變時才會被「觸發」，
並在delay 40ns以後，才去做nor的動作嗎？
且其在執行時，所看的input的值，都是在執行當下的值嗎？
例如nor在150ns時執行，而它要看的是150ns的w1和E的值。
（用「觸發」這個詞好像有點不恰當，希望你能明白我的意思……）

2. 所以在我這個例子中，delay的意義是體現在於，
當input有所改變後，要「delay」若干ns才執行動作，
而不是input的值要「delay」若干ns後，才進gate中去執行動作。
我這樣理解是否正確？

3. 如果我把我例子中的or的#(30)改為#(50)，會得到下面這張波形圖：
https://i.imgur.com/gHjkfBk.png

想請問在這張波形圖中，w1也剛好在150ns時從0變成1，
那麼在150ns要做nor時，為什麼取到的w1的值是0？而不是1？

不好意思，問題有點多……
再次感謝你的回答！

→ furio: 請問是用什麼跑出來的? 11/07 18:10

我用的simulator是ncverilog，
不好意思我是初學，不知道你要問的是不是這個？
※ 編輯: Emeth (123.195.36.40), 11/07/2018 21:32:22
※ 編輯: Emeth (123.195.36.40), 11/07/2018 21:33:18

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Delay models. Three types of delay models used in Verilog. Distributed delay model. Lumped Delay model. Pin-to-pin (path) Delay ...

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#87Verilog 語法(2012/04/10) @ Mark的部落格 - 隨意窩

ANS: `timescale 1ns/100ps #10”, 表示delay 10 ns.2. ... 還是Testbench 及Verilog Source 兩者都可以用? ANS: 都要. 但只有在simulation才有效.

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#88Verilog Tutorial II

Verilog. Delay Modeling in Verilog. – Assignment Delay. – Hold and setup time checks. Tristate Buffers and Busses in Verilog. – Schematic Example. – Verilog ...

於www.cs.utexas.edu
#89Help with adding delay in Verilog : r/FPGA - Reddit

Beginner here . Can someone please explain how do I add delay to my synthesized program in Verilog because the # function cannot be ...

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#90Verilog-A Functions - SIMPLIS

Verilog -A Functions ... The Verilog-A language reference manual does not define the codes that this ... Applies a transport delay to an input signal.

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#91我想問如何在Quartus II上產生傳播延遲，使用verilog #10寫法 ...

Propagation delays in Verilog like #10 are non-synthesizable and Quartus ignores delays coded in Verilog. If you really need to introduce a delay in a ...

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#92對Verilog 初學者比較有用的整理 - 程式前沿

所謂綜合，就是把描述語言轉化成能硬體實現的電路，學verilog的時候，沒有人給我說 ... Clock Period = Clk-to-out Data Delay Setup Time – Clk Skew

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#93Inertial and transport delay in Verilog - Computer ...

I am learning Verilog. However, I have a fair knowledge of VHDL. VHDL provides two delay models - inertial and transport delay models.

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#94Digital Design - UCSD CSE

What we covered thus far: – Appendix A,B, Chap. 1-6. – Transistors, delay. – Verilog HDL for combinational circuits. • Lab #1 graded, Lab #2 due next week.

於cseweb.ucsd.edu
#95Digital VLSI Design with Verilog: A Textbook from Silicon ...

Chapter 9 Week 5 Class 1 9.1 Rise-Fall Delays and Event Scheduling This time we shall look into delays, timing, and the way they are used in verilog ...

於books.google.com.tw
#96Verilog HDL: A Guide to Digital Design and Synthesis

Min , typ , or max values can be chosen at Verilog run time . ... If no option is specified , the typical delay value is the default ) .

於books.google.com.tw
#97Introduction to Verilog

Procedural Assignments, Delay in Assignment, Blocking and ... More recently Verilog is used as an input for synthesis programs which will ...

於www.cse.wustl.edu
#98Design and Delay Analysis of Various 256-Bit Adders using ...

Design and Delay Analysis of Various 256-Bit Adders using Verilog - written by Rachana S, Ritu Patil, Sahana V published on 2020/08/04 ...

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#99Control unit verilog code

control unit verilog code We do so, by designing the following control module with 6 ... I A module should be contained within one le Verilog Delay Control.

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