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並前往https://developer.arm.com/documentation/ddi0489/b/system-control/register-descriptions/l1-cache-control-register

L1 Cache Control Register - ARM Cortex-M7 Processor ...

L1 Cache Control Register. The CM7_CACR characteristics are: Purpose. Controls the L1 ECC and the L1 cache coherency usage model. Usage Constraints.

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