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並前往https://course.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=goodrtl-parkin.pdf

Writing Successful RTL Descriptions in Verilog

decoder using shift operator module decoder32V2(adr, decode); input [4:0] adr; output [31:0] decode; assign decode = ~(1'b1 << adr); endmodule.

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