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並前往https://people.ece.cornell.edu/land/courses/ece5760/Verilog/LatticeTestbenchPrimer.pdf

A Verilog HDL Test Bench Primer - Cornell ECE

example, the clock to the counter is called clk in count16, but in the test ... a #5 or #1 in a Verilog assignment to be a 5 ns or 1 ns delay respectively.

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