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並前往http://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/verilog_operators.pdf

Verilog - Operators - Oregon State University

//if a is less than b, output is logic one module less8( input [7:0] a,b, output z. ); assign z = (a < b) ? 1'b1 : 1'b0; endmodule. Results from synthesis:.

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