你即將離開本站

並前往https://patents.google.com/patent/US7436043B2/en

N-well and N+ buried layer isolation by auto doping to reduce ...

N + buried layers are required for high voltage PMOS and isolated high voltage NMOS devices. If LVNW areas of different potentials contact a common NBL, then ...

確定！ 回上一頁

查詢 「NBL layer in CMOS」的人也找了：

  1. n buried layer purpose
    2.
  2. buried layer意思
    3.