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並前往https://www.ece.ucdavis.edu/~ramirtha/EEC116/F11/lecture5.pdf

EEC 116 Lecture #5: CMOS Logic - HiBuS® Technology

CMOS Gates: Equivalent Inverter. • Represent complex gate as inverter for delay estimation. • Typically use worst-case delays. • Example: NAND gate.

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