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並前往https://www.intel.com/content/www/us/en/docs/programmable/683584/current/855829-reads-of-pmevcntr-n-are-not-masked.html

Reads of PMEVCNTR are not Masked by HDCR.HPMN

Software executing at EL2 can set the HDCR.TPM and MDCR_EL2.TPM bit. This configuration causes all non-secure EL0 and EL1 accesses to performance monitor ...

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