你即將離開本站

並前往https://www.edaboard.com/threads/is-it-legal-to-use-always-block-inside-verilog-generate-for.311074/

Is it legal to use always block inside verilog "generate for"

is it legal to have always block inside a "generate for" statement as shown above ? is this synthesizable ? what will be the synthesis result ?

確定！ 回上一頁

查詢 「Generate block」的人也找了：

  1. Verilog generate block
    2.
  2. Verilog generate block name
    3.
  3. Generate block
    4.
  4. generate blocks in verilog
    5.
  5. SystemVerilog generate
    6.
  6. Verilog generate always
    7.
  7. verilog generate用法
    8.
  8. Verilog generate module
    9.