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並前往http://vlsi.hongik.ac.kr/lecture/%EC%9D%B4%EC%A0%84%20%EA%B0%95%EC%9D%98%20%EC%9E%90%EB%A3%8C/vlsi/2_lect5_Logical_Effort_Rabaey_33.pdf

Logical Effort (Sizing Staging Fan out)

i.e., the delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan out f.

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