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並前往https://training.ti.com/sites/default/files/docs/Running_RTOS_on_Cortex_M4_SLIDES.pdf

Running TI-RTOS on the ARM CortexTM-M4 Processor

Each IPU subsystem contains two ARM. Cortex-M4 processor cores: – IPUx_C0. – IPUx_C1. • The two IPUx cores share a common Level 1 (L1) cache: IPUx_UNICACHE.

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