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並前往https://community.intel.com/t5/Programmable-Devices/error-10170-HDL-syntax-error-in-Verilog/td-p/171659

error 10170: HDL syntax error in Verilog - Intel Communities

I solved that error! :) we should declare always(posedge...) instead of always (edge...) in Verilog. :).

確定！ 回上一頁

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